As the speed of computer processors increases, the need for high-speed computer memory also increases. One high-speed computer memory is Synchronous Dynamic Random Access Memory (SDRAM). To increase speed, SDRAM transactions include both command operations (PRECHARGE to close and ACTIVATE to open rows in memory banks) and data operations (READ and WRITE). This protocol is part of a JEDEC (Joint Electron Device Engineering Council) standard that is followed by the semiconductor industry. Many early memory controllers service READ/WRITE requests in the same order as they are received, and at the same time, serializes the command and data operations.
With the widening performance gap between processors and memory, other approaches have been used in memory controllers to speed up the SDRAM command and data operations. In one approach, the command and data operations are classified as background and foreground commands, allowing them to be pipelined or overlapped in time. In another approach, a queue-based method is used where each memory request is broken into primitives to issue command and data operations, thereby allowing the operations to overlap because the primitives can overlap. In a still further approach, READ and WRITE operations are placed in separate ‘CAS’ (Column Address Strobe) queues, thereby reordering their time of issue. This scheme can be considered a finer definition of the primitives, and is done in order to reduce the overhead of command operations. More recently, the queue-based approach has been extended by interleaving memory requests from multiple sources/requestor.
In a different approach, memory requests from multiple sources are dynamically scheduled. Unlike previously discussed memory controllers, each requestor (such as the CPU, DMA and LCD controller) can issue many pending requests, and the memory controller is allowed to service them in any order because the source maintains strict memory coherency. This split/request bus is recently becoming popular because it allows slow peripherals (and external memory can be slow) to service critical requests first. Similar features of this scheme have been adopted as an industry standard in the AMBA™ (Advanced Microcontroller Bus Architecture) bus protocol.
Current high bandwidth memory controllers are typically built to interleave command operations (PRECHARGE to close and ACTIVATE to open rows in memory banks) with data operations (READ and WRITE), but they are not designed to dynamically reorganize the order of the requests to utilize the maximum memory bandwidth more efficiently and to reduce command operation overheads. They lack support for advanced split request buses, where there can be many pending requests from a single source/requestor (e.g. CPU). Furthermore, these memory controllers lack feedback mechanisms for the operating system or applications to better control how much bandwidth is allocated for a particular source/requestor.